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SCAN182245A Non-Inverting Transceiver with 25 Series Resistor Outputs
December 1993 Revised January 2001
SCAN182245A Non-Inverting Transceiver with 25 Series Resistor Outputs
General Description
The SCAN182245A is a high performance BiCMOS bidirectional line driver featuring separate data inputs organized into dual 9-bit bytes with byte-oriented output enable and direction control signals. This device is compliant with IEEE 1149.1 Standard Test Access Port and Boundary Scan Architecture with the incorporation of the defined boundary-scan test logic and test access port consisting of Test Data Input (TDI), Test Data Out (TDO), Test Mode Select (TMS), and Test Clock (TCK).
Features
s High performance BiCMOS technology s 25 series resistors in outputs eliminate the need for external terminating resistors s Dual output enable control signals s 3-STATE outputs for bus-oriented applications s 25 mil pitch SSOP (Shrink Small Outline Package) s IEEE 1149.1 (JTAG) Compliant s Includes CLAMP, IDCODE and HIGHZ instructions s Additional instructions SAMPLE-IN, SAMPLE-OUT and EXTEST-OUT s Power Up 3-STATE for hot insert s Member of Fairchild's SCAN Products
Ordering Code:
Order Number SCAN182245ASSC SCAN182245AMTD Package Number MS56A MTD56 Package Description 56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118, 0.300 Wide 56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter "X" to the ordering code.
Connection Diagram
Pin Descriptions
Pin Names A1(0-8) B1(0-8) A2(0-8) B2(0-8) G1, G2 DIR1, DIR2 Description Side A1 Inputs or 3-STATE Outputs Side B1 Inputs or 3-STATE Outputs Side A2 Inputs or 3-STATE Outputs Side B2 Inputs or 3-STATE Outputs Output Enable Pins (Active LOW) Direction of Data Flow Pins
(c) 2001 Fairchild Semiconductor Corporation
DS011657
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SCAN182245A
Truth Tables
Inputs G1 (Note 1) L L L L H
H = HIGH Voltage Level L = LOW Voltage Level
Inputs DIR1 L L H H X A1(0-8) H L H L Z B1(0-8) G2 (Note 1) L L L L H
X = Immaterial Z = High Impedance
DIR2 L L H H X
A2(0-8) H L H L Z
B2(0-8)

H L H L Z

H L H L Z
Note 1: Inactive-to-Active transition must occur to enable outputs upon power-up.
Functional Description
The SCAN182245A consists of two sets of nine non-inverting bidirectional buffers with 3-STATE outputs and is intended for bus-oriented applications. Direction pins (DIR1 and DIR2) LOW enables data from B Ports to A Ports, when HIGH enables data from A Ports to B Ports. The Output Enable pins (G1 and G2) when HIGH disables both A and B Ports by placing them in a high impedance condition.
Block Diagrams
A1, B1, G1 and DIR1 A2, B2, G2 and DIR2
Note: BSR stands for Boundary Scan Register.
Note: BSR stands for Boundary Scan Register.
Tap Controller
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SCAN182245A
Description of BOUNDARY-SCAN Circuitry
The scan cells used in the BOUNDARY-SCAN register are one of the following two types depending upon their location. Scan cell TYPE1 is intended to solely observe system data, while TYPE2 has the additional ability to control system data. Scan cell TYPE1 is located on each system input pin while scan cell TYPE2 is located at each system output pin as well as at each of the two internal active-high output enable signals. AOE controls the activity of the A-outputs while BOE controls the activity of the B-outputs. Each will activate their respective outputs by loading a logic high. The BYPASS register is a single bit shift register stage identical to scan cell TYPE1. It captures a fixed logic low. Bypass Register Scan Chain Definition Logic 0 The INSTRUCTION register is an 8-bit register which captures the default value of 10000001 (SAMPLE/PRELOAD) during the CAPTURE-IR instruction command. The benefit of capturing SAMPLE/PRELOAD as the default instruction during CAPTURE-IR is that the user is no longer required to shift in the 8-bit instruction for SAMPLE/PRELOAD. The sequence of: CAPTURE-IR EXIT1-IR UPDATE-IR will update the SAMPLE/PRELOAD instruction. For more information refer to the section on instruction definitions. Instruction Register Scan Chain Definition
MSB LSB Instruction Code 00000000 10000001 10000010 00000011 Instruction EXTEST SAMPLE/PRELOAD CLAMP HIGH-Z SAMPLE-IN SAMPLE-OUT EXTEST-OUT IDCODE BYPASS BYPASS
SCAN182245A Product IDCODE (32-Bit Code per IEEE 1149.1) Versio n 0000 MSB Entity Part Number Manufacture r ID Required by 1149.1 1 MSB
01000001 01000010 00100010 10101010 11111111 All Others
111111 000000000 00000001111 0
Scan Cell TYPE1
Scan Cell TYPE2
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SCAN182245A
Description of BOUNDARY-SCAN Circuitry
(Continued) BOUNDARY-SCAN Register Scan Chain Definition (80 Bits in Length)
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SCAN182245A
Description of BOUNDARY-SCAN Circuitry
(Continued) Input BOUNDARY-SCAN Register Scan Chain Definition (40 Bits in Length) When Sample In is Active
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SCAN182245A
Description of BOUNDARY-SCAN Circuitry
(Continued) Output BOUNDARY-SCAN Register Scan Chain Definition (40 Bits in Length) When Sample Out and EXTEST-Out are Active
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SCAN182245A
Description of BOUNDARY-SCAN Circuitry
Bit No. Pin Name Pin No. Pin Type Scan Cell Type 79 DIR1 78 G1 77 AOE1 76 BOE1 75 DIR2 74 G2 73 AOE2 72 BOE2 71 A10 70 A11 69 A12 68 A13 67 A14 66 A15 65 A16 64 A17 63 A18 62 A20 61 A21 60 A22 59 A23 58 A24 57 A25 56 A26 55 A27 54 A28 53 B10 52 B11 51 B12 50 B13 49 B14 48 B15 47 B16 46 B17 45 B18 44 B20 43 B21 42 B22 41 B23 40 B24 39 B25 38 B26 37 B27 36 B28 55 53 52 50 49 47 46 44 43 42 41 39 38 36 35 33 32 30 2 4 5 7 8 10 11 13 14 15 16 18 19 21 22 24 25 27 26 31 3 54 Input Input Internal Internal Input Input Internal Internal Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output TYPE1 TYPE1 TYPE2 TYPE2 Control TYPE1 Signals TYPE1 TYPE2 TYPE2 TYPE1 TYPE1 TYPE1 TYPE1 TYPE1 A1-in TYPE1 TYPE1 TYPE1 TYPE1 TYPE1 TYPE1 TYPE1 TYPE1 TYPE1 A2-in TYPE1 TYPE1 TYPE1 TYPE1 TYPE2 TYPE2 TYPE2 TYPE2 TYPE2 B1-out TYPE2 TYPE2 TYPE2 TYPE2 TYPE2 TYPE2 TYPE2 TYPE2 TYPE2 B2-out TYPE2 TYPE2 TYPE2 TYPE2
(Continued) BOUNDARY-SCAN Register Definition Index Bit No. Pin Name Pin No. Pin Type Scan Cell Type 35 B10 34 B11 33 B12 32 B13 31 B14 30 B15 29 B16 28 B17 27 B18 26 B20 25 B21 24 B22 23 B23 22 B24 21 B25 20 B26 19 B27 18 B28 17 A10 16 A11 15 A12 14 A13 13 A14 12 A15 11 A16 10 A17 9 A18 8 A20 7 A21 6 A22 5 A23 4 A24 3 A25 2 A26 1 A27 0 A28 2 4 5 7 8 10 11 13 14 15 16 18 19 21 22 24 25 27 55 53 52 50 49 47 46 44 43 42 41 39 38 36 35 33 32 30 Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output TYPE1 TYPE1 TYPE1 TYPE1 TYPE1 TYPE1 TYPE1 TYPE1 TYPE1 TYPE1 TYPE1 TYPE1 TYPE1 TYPE1 TYPE1 TYPE1 TYPE1 TYPE1 TYPE2 TYPE2 TYPE2 TYPE2 TYPE2 A1-out TYPE2 TYPE2 TYPE2 TYPE2 TYPE2 TYPE2 TYPE2 TYPE2 TYPE2 A2-out TYPE2 TYPE2 TYPE2 TYPE2 B2-in B1-in
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SCAN182245A
SCAN ABT Live Insertion and Power Cycling Characteristics
SCAN ABT is intended to serve in Live Insertion backplane applications. It provides 2nd Level Isolation1 which indicates that while external circuitry to control the output enable pin is unnecessary, there may be a need to implement differential length backplane connector pins for VCC and GND. As well, pre-bias circuitry for backplane pins may be necessary to avoid capacitive loading effects during live insertion. SCAN ABT provides control of output enable pins during power cycling via the circuit in Figure 1. It essentially controls the Gn pin until VCC reaches a known level. During power-up, when VCC ramps through the 0.0V to 0.7V range, all internal device circuitry is inactive, leaving output and I/O pins of the device in high impedance. From approximately 0.8V to 1.8V VCC, the Power-On-Reset circuitry, (POR), in Figure 1 becomes active and maintains device high impedance mode. The POR does this by providing a low from its output that resets the flip-flop The output, Q, of the flip-flop then goes high and disables the NOR gate from an incidental low input on the Gn pin. After 1.8V VCC, the POR circuitry becomes inactive and ceases to control the flip-flop. To bring the device out of high impedance, the Gn input must receive an inactive-to-active transition, a high-to-low transition on Gn in this case to change the state of the flip-flop. With a low on the Q output of the flip-flop, the NOR gate is free to allow propagation of a Gn signal. During power-down, the Power-On-Reset circuitry will become active and reset the flip-flop at approximately 1.8V VCC. Again, the Q output of the flip-flop returns to a high and disables the NOR gate from inputs from the Gn pin. The device will then remain in high impedance for the remaining ramp down from 1.8V to 0.0V VCC. Some suggestions to help the designer with live insertion issues: * The Gn pin can float during power-up until the PowerOn-Reset circuitry becomes inactive. * The Gn pin can float on power-down only after the Power-On-Reset has become active. The description of the functionality of the Power-On-Reset circuitry can best be described in the diagram of Figure 2.
FIGURE 1.
1
Section 7, "Design Consideration for Fault Tolerant Backplanes", Application Note AN-881.
SCAN ABT includes additional power-on reset circuitry not otherwise included in ABT devices.
FIGURE 2.
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SCAN182245A
Absolute Maximum Ratings(Note 2)
Storage Temperature Ambient Temperature under Bias Junction Temperature under Bias VCC Pin Potential to Ground Pin Input Voltage (Note 3) Input Current (Note 3) Voltage Applied to Any Output in the Disabled or Power-Off State in the HIGH State Current Applied to Output in LOW State (Max) DC Latchup Source Current Over Voltage Latchup (I/O) ESD (HBM) Min. Twice the Rated IOL (mA)
-65C to +150C -55C to +125C -55C to +150C -0.5V to +7.0V -0.5V to +7.0V -30 mA to +5.0 mA
Recommended Operating Conditions
Free Air Ambient Temperature Supply Voltage Minimum Input Edge Rate Data Input Enable Input
-40C to +85C +4.5V to +5.5V
(V/t) 50 mV/ns 20 mV/ns
-0.5V to +5.5V -0.5V to VCC
Note 2: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied. Note 3: Either voltage limit or current limit is sufficient to protect inputs.
-500 mA
10V 2000V
DC Electrical Characteristics
Symbol VIH VIL VCD VOH VOL IIH Parameter Input HIGH Voltage Input LOW Voltage Input Clamp Diode Voltage Output HIGH Voltage Output LOW Voltage Input HIGH Current All Others TMS, TDI IBVI IBVIT IIL Input HIGH Current Breakdown Test Input HIGH Current Breakdown Test (I/O) Input LOW Current All Others TMS, TDI VID IIH + IOZH IIL + IOZL IOZH IOZL IOS ICEX IZZ ICCH ICCL ICCZ ICCT Input Leakage Test Output Leakage Current Output Leakage Current Output Leakage Current Output Leakage Current Output Short-Circuit Current Output HIGH Leakage Current Bus Drainage Test Power Supply Current Power Supply Current Power Supply Current Additional ICC/Input All Other Inputs TDI, TMS inputs ICCD Dynamic ICC No Load Max Max Max 2.9 3 0.2 mA mA mA/ MHz
Note 4: Guaranteed not tested.
VCC
Min 2.0
Typ
Max 0.8
Units V V V V V
Conditions Recognized HIGH Signal Recognized LOW Signal IIN = -18 mA IOH = -3 mA IOH = -32 mA IOL = 15 mA VIN = 2.7V (Note 4) VIN = VCC VIN = VCC VIN = 7.0V VIN = 5.5V VIN = 0.5V (Note 4) VIN = 0.0V VIN = 0.0V IID = 1.9 A All Other Pins Grounded VOUT = 2.7V VOUT = 0.5V VOUT = 2.7V VOUT = 0.5V VOUT = 0.0V VOUT = VCC VOUT = 5.5V, All Others GND VOUT = VCC; TDI, TMS = VCC VOUT = VCC; TDI, TMS = GND VOUT = LOW; TDI, TMS = VCC VOUT = LOW; TDI, TMS = GND TDI, TMS = VCC TDI, TMS = GND VIN = VCC - 2.1V VIN = VCC - 2.1V Outputs Open One Bit Toggling, 50% Duty Cycle
Min Min Min Min Max Max Max Max Max Max Max Max 0.0 Max Max Max Max Max Max 0.0 Max Max Max Max Max Max -100 4.75 2.5 2.0
-1.2
0.8 5 5 5 7 100 -5 -5 -385
V A A A A A A A A V
50 -50 50 -50 -275 50 100 250 1.0 65.8 250 1.0
A A A A mA A A A mA mA mA A mA
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SCAN182245A
AC Electrical Characteristics
Normal Operation: VCC Symbol Parameter (V) (Note 5) tPLH tPHL tPLZ tPHZ tPZL tPZH
Note 5: Voltage Range 5.0V 0.5V
TA = -40C to +85C CL = 50 pF Min 1.0 1.5 1.5 1.5 1.5 1.5 Typ 3.1 4.4 4.8 5.2 5.5 4.6 Max 5.2 6.5 8.6 8.9 9.1 8.2 ns ns ns Units
Propagation Delay A to B, B to A Disable Time Enable Time
5.0 5.0 5.0
AC Electrical Characteristics
Scan Test Operation VCC Symbol Parameter (V) (Note 6) tPLH tPHL tPLZ tPHZ tPZL tPZH tPLH tPHL tPLH tPHL tPLH tPHL tPLZ tPHZ tPLZ tPHZ tPLZ tPHZ tPZL tPZH tPZL tPZH tPZL tPZH Propagation Delay TCK to TDO Disable Time TCK to TDO Enable Time TCK to TDO Propagation Delay TCK to Data Out during Update-DR State Propagation Delay TCK to Data Out during Update-IR State Propagation Delay TCK to Data Out during Test Logic Reset State Disable Time TCK to Data Out during Update-DR State Disable Time TCK to Data Out during Update-IR State Disable Time TCK to Data Out during Test Logic Reset State Enable Time TCK to Data Out during Update-DR State Enable Time TCK to Data Out during Update-IR State Enable Time TCK to Data Out during Test Logic Reset State 5.0 5.0 5.0 5.0 5.0 5.0 5.0 5.0 5.0 5.0 5.0 5.0 Min 2.9 4.2 2.1 3.3 4.6 2.8 2.8 4.5 3.3 5.0 3.7 5.7 2.8 3.5 3.6 3.8 4.0 4.2 4.4 3.0 5.2 3.9 5.7 3.0 TA = -40C to +85C CL = 50 pF Typ 6.1 7.7 5.9 7.4 8.7 6.8 6.3 8.2 7.2 9.3 8.4 10.8 7.6 8.4 8.7 9.2 9.8 9.9 9.3 7.5 10.7 9.0 12.0 10.2 Max 10.2 12.1 10.7 12.5 13.7 11.5 10.7 13.0 12.2 14.8 14.0 17.2 13.9 14.5 15.1 15.9 17.1 16.6 15.5 13.3 17.4 15.4 19.8 17.6 ns ns ns ns ns ns ns ns ns ns ns ns Units
Note 6: Voltage Range 5.0V 0.5V Note: All Propagation Delays involving TCK are measured from the falling edge of TCK.
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SCAN182245A
AC Operating Requirements
Scan Test Operation VCC Symbol Parameter (V) (Note 7) tS tH tS tH tS tH tS tH tS tH tS tH tW fMAX tPU tDN Setup Time Data to TCK (Note 8) Hold Time Data to TCK (Note 8) Setup Time, H or L G1, G2 to TCK (Note 9) Hold Time, H or L TCK to G1, G2 (Note 9) Setup Time, H or L DIR1, DIR2 to TCK (Note 10) Hold Time, H or L TCK to DIR1, DIR2 (Note 10) Setup Time Internal OE to TCK (Note 11) Hold Time, H or L TCK to Internal OE (Note 10) Setup Time, H or L TMS to TCK Hold Time, H or L TCK to TMS Setup Time, H or L TDI to TCK Hold Time, H or L TCK to TDI Pulse Width TCK: Maximum TCK Clock Frequency Wait Time, Power Up to TCK Power Down Delay
Note 7: Voltage Range 5.0V 0.5V Note 8: Timing pertains to the TYPE1 BSR and TYPE2 BSR after the buffer (BSR 0-8, 9-17, 18-26, 27-35, 36-44, 45-53, 54-62, 63-71). Note 9: Timing pertains to BSR 74 and 78 only. Note 10: Timing pertains to BSR 75 and 79 only. Note 11: Timing pertains to BSR 72, 73, 76 and 77 only. Note: All Input Timing Delays involving TCK are measured from the rising edge of TCK.
TA = -40C to +85C CL = 50 pF Guaranteed Minimum 4.8 2.5 4.1 1.7 4.2 2.3 3.8 2.3 8.7 1.5 6.7 5.0 10.2 8.5 50 100 100 ns ns ns ns ns ns ns ns ns ns ns ns ns MHz ns ms Units
5.0 5.0 5.0 5.0 5.0 5.0 5.0 5.0 5.0 5.0 5.0 5.0 H L 5.0 5.0 5.0 0.0
Capacitance
Symbol CIN CI/O (Note 12) Parameter Input Capacitance Output Capacitance Typ 5.9 13.7 Units pF pF Conditions, TA = 25C VCC = 0.0V (Gn, DIRn) VCC = 5.0V (An, Bn)
Note 12: CI/O is measured at frequency f = 1 MHz, per MIL-STD-883B, Method 3012.
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SCAN182245A
Physical Dimensions inches (millimeters) unless otherwise noted
56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118, 0.300 Wide Package Number MS56A
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SCAN182245A Non-Inverting Transceiver with 25 Series Resistor Outputs
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide Package Number MTD56
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 13 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com
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